The TMS320VC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the 5402 unless
otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus
and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of
parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis
of the operational flexibility and speed of this DSP is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing the
high degree of parallelism. Two read operations and one write operation can be performed in a single cycle.
Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition,
data can be transferred between data and program spaces. Such parallelism supports a powerful set of
arithmetic, logic, and bit-manipulation operations that can be performed in a single machine cycle. In addition,
the 5402 includes the control mechanisms to manage interrupts, repeated operations, and function calls.