The AD9434 is a 12-bit monolithic sampling analog-to-digital converter (ADC) optimized for high performance, low power, and ease of use. The part operates at up to a 500 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution. This reference design includes a data capture interface and the external DDR-DRAM interface for sample storage. It allows programming the device and monitoring it's internal status registers. The board also provides other options to drive the clock and analog inputs of the ADC.

• AD9434-FMC-500EBZ

The reference design is built on a Zynq based system parameterized for linux. It consists of three functional modules, a LVDS interface, a PN monitor and a DMA interface. The LVDS interface captures and buffers data from the ADC. The data is captured using ISERDES primitives and is captured 4 samples wide at 1/4th of the ADC clock (125MHz at 500MHz ADC clock). The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software. By default, the board is configured to use the onboard clock.

• ZC706 LPC Slot
• ML605 Legacy

Board Files:

The reference design has been tested with ML605. It should be easily portable to other boards such as KC705 and VC707, only the ISERDES primitive, UCF and MHS files need to be changed. The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT). This bit file configuration also captures the test mode outputs of ADC.

• ML605 board
• AD9434-FMC board (the default setup uses onboard clock)
• Signal generator (for data)

• Xilinx ISE (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). Use the latest version or the one used in the reference design.
• A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.
• Xilinx Chipscope Analyzer (for signal capture plot).

To begin, connect the AD9434-FMC board to the FMC-LPC connector of ML605 board (see image below). Connect power and two USB cables from the PC to the JTAG and UART USB connectors on the edge of the ML605. The demo program uses the default board configuration that uses an on-board clock. Connect a signal source to the AIN SMA (J100) connector of the FMC card. After the hardware setup, turn the power on to the ML605.

Start IMPACT, and initialize the JTAG chain. The program should recognize the Virtex 6 device. Start a UART terminal (set to 57600 baud rate) and then program the device. If programming was successful, you should be seeing messages appear on the terminal as shown in the figure below. After reading some default registers in the AD9434 and AD9517, the program enables different test patterns available on the ADC.

After patterns and prbs sequences are verified, if no errors are present, you may use the chipscope busplot to see the captured signal (see below). The ADC data is available 4-samples wide at 125MHz. The most recent sample is at the most significant bits of the captured data.

The reference design is built on a microblaze based system parameterized for linux. It consists of three functional modules, a LVDS interface, a PN monitor and a DMA interface. The LVDS interface captures and buffers data from the ADC. The data is captured using ISERDES primitives and is captured 4 samples wide at 1/4th of the ADC clock (125MHz at 500MHz ADC clock). The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.

Refer to the regmap.txt file inside the pcores directory.

The board provides different (some modification maybe necessary) possible clock path for clocking the AD9434.

FPGA Referece Designs:

Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See generating Xilinx netlist/verilog files from xco files for details.

The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to Xilinx EDK documentation for details.