The CY7C1350G is a 3.3 V， 128K × 36 synchronous-pipelined burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency? （NoBL?） logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM， especially in systems that require frequent write/read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the clock enable （CEN） signal， which， when deasserted， suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 2.8 ns （200-MHz device）。 Write operations are controlled by the four byte write select （BW［A:D］） and a write enable （WE） input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous chip enables （CE1， CE2， CE3） and an asynchronous output enable （OE） provide for easy bank selection and output tristate control. In order to avoid bus contention， the output drivers are synchronously tri-stated during the data portion of a write sequence. For a complete list of related documentation， click here.