The CY7C1354C/CY7C1356C［1］ are 3.3 V， 256K × 36/512K × 18 synchronous pipelined burst SRAMs with No Bus Latency? （NoBL?） logic， respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1354C/CY7C1356C are equipped with the advanced （NoBL） logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature greatly improves the throughput of data in systems that require frequent write/read transitions. The CY7C1354C/CY7C1356C are pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the clock enable （CEN） signal， which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the byte write selects （BWa–BWd for CY7C1354C and BWa–BWb for CY7C1356C） and a write enable （WE） input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous chip enables （CE1， CE2， CE3） and an asynchronous output enable （OE） provide for easy bank selection and output tristate control. To avoid bus contention， the output drivers are synchronously tristated during the data portion of a write sequence. For a complete list of related documentation， click here.